As computers and computer processors increase in performance, memory access performance becomes a significant factor affecting overall system performance. If an interface that communicates data between a memory device and a memory controller or other application device operates more slowly than a processor can use data, the interface can reduce the data processing capacity of the entire computer. For dynamic random access memory (DRAM) devices, which are commonly used as the main working memory for a computer, various interconnect technologies have been developed over the years. One such interconnect technology is used for synchronous DRAMs, or SDRAMs, which utilize a source synchronous interface, where the source of data during a data transfer is relied upon to provide a data strobe signal that is used by the target of the data transfer to capture such data as it is being transferred over a data line to the target. In particular, the capture of data on a data line is typically latched by the rising or falling edge of the data strobe signals, for example, so that the value transmitted on a data line when the data strobe signal transitions from low to high, or vice-versa, will be latched into a data latch in the target.
DRAM memory elements, such as double data rate (DDR) memory elements, contain multiple buses. A command and address bus is formed by a number of signals, such as, for example, a column-address strobe (CAS), row-address strobe (RAS), write enable (WE), clock enable (CKE), chip-select (CS), address (ADDR), bank address (BA) signals, and differential clock signals (CK and CKN). DDR3 memory elements operate with differential data strobe signals DQS and DQSN, which enable source synchronous data capture at twice the clock frequency. The data bus between the host logic circuitry and the DRAM includes the data signals (DQ) and data strobe signals (DQS and DQSN).
In DDR3 DRAM systems, data is transferred in bursts for both read and write operations, sending or receiving a series of four (referred to as burst chop 4 or BC4) or eight (referred to as burst length 8 or BL8) data words with each memory access. For read operations, data bursts of various lengths are transmitted by the DRAM edge-aligned with a data strobe signal. For write operations, data bursts of various lengths are received by the DRAM element with a 90-degree phase-delayed data strobe signal. The one or more data strobe signal lines between the host logic circuitry and the DRAM are bidirectional. The data strobe signal issued by the DRAM is used by the host logic circuitry to capture data during read operations. The data strobe signal issued by the host logic circuitry is used by the DRAM to capture data during write operations.
When the data bus is inactive, i.e., no data is being transferred, the data strobe signal lines assume a tristate or termination voltage level VTT that, for DDR3 DRAM systems, is one-half the supply voltage VDD. The termination voltage thus defines neither a logic-0 nor a logic-1 level. In a read operation, the host logic circuitry issues a read command and communicates a clock signal to the source DRAM. In response to the read command, and after a DRAM internal delay, the DRAM causes the data strobe signal lines to change state from the termination voltage to a “preamble” state that, for DDR3 DRAM systems, is a logic-0 level with a duration of a full cycle of the DRAM clock, or two cycles of CLK—2X. Following the preamble, the DRAM issues one or more bursts of data accompanied by the requisite data strobe signals. The host logic circuitry may use the preamble to prepare itself to receive the data. The host logic circuitry uses the data strobe signals to capture or register the data. The host logic circuitry registers the incoming data signals with the rising edges of the differential data strobe signals, i.e., the rising edges of both DQS and DQSN.
The host logic circuitry includes differential receivers to receive the data strobe signals. When both inputs of a differential receiver are driven to the termination voltage level VTT, the output of the differential receiver is undefined. If the undefined output were allowed to propagate to logic that handles incoming data, spurious edges on the data strobe signals could cause erroneous results. Therefore, the host logic circuitry commonly includes “parking” logic to force the output of the differential data strobe signal receivers to a defined logic value until the preamble arrives. The parking logic un-parks the data strobe signal during the preamble and then re-parks the data strobe signal during the postamble. The preamble thus serves as a window in which to un-park the differential data strobe signal receiver outputs. It is generally desirable to un-park the differential data strobe signal receiver outputs in the middle of the preamble. Therefore, methods have been developed to generate a parking control signal or preamble release signal that goes active in the middle of the preamble. Such methods include feedback-based training methods that seek the optimal delay value for a programmable delay element to delay activation of the parking control signal until the middle of the preamble.
A known training method involves setting or programming the programmable delay value and issuing a read command. In response to the read command, a pulse is propagated through the programmable delay element and thus delayed. The parking logic uses this delayed pulse as a preamble release signal to un-park the data strobe signal. When the memory responds to the read command by activating the data strobe signal (i.e., transitioning from the termination voltage to a preamble followed by a number of data strobe signal transitions), the incoming data strobe signal is sampled with a register clocked by the preamble release signal. If the data strobe signal is sampled during the preamble, the sampling register will sample or capture a logic-0. If the data strobe signal is sampled just after the first data strobe signal edge, the sampling register will sample or capture a logic-1. The procedure is repeated in an iterative manner, setting a different delay value on each iteration. From the results captured in the sampling register, an optimum delay value that places the preamble release signal in the middle of the preamble can be computed.
After the training method has been completed and the programmable delay element has been set to the optimal value, drift in the timing relationship between the host logic circuitry and the DRAM can cause the preamble release signal to lose alignment with the middle of the preamble. Periodically re-training the preamble release signal is possible but not an optimal solution because it requires periodically halting the memory system.